RadPix brainstorming - Open questions Room: 337 - In-pixel digital readout (ie hit buffers) inside the pixel (like in RD50-MPW4) or at the periphery (like MightyPix/LF-MightyPix) - pros and cons of each configuration - LHCb requires 32-bit data words: RD50-MPW4 has 8-bit time-stamps, is this enough to achieve the required 3 ns time resolution? How many bits to address rows and columns in a 2 cm x 2 cm chip (RD50-MPW4 has 8-bit row address and 8-bit column address) - How many FIFOs in the periphery given the data rate anticipated in Mighty Tracker and UP, to avoid loosing hits - Pixel size will mostl likely be 100 um x 100 um, anticipate how this will benefit power consumption (distribute allowed power budget between pixel matrix and everything else) - Plan to develop and evaluate enclosed layout transistors - Voltage regulation

Lunch break Room: 337

RadPix chip block diagram Room: 337 - Sketch block diagram, think of main specs for all the main blocks, and estimate what 'should' be included in RadPix1/can be realistically designed until the chip submission

RadPix submission plan Room: 337 - Anticipated timeline for submissions - What blocks are included in each submission - Who designs what block - Person power and submission funding - Design files sharing

Coffee break Room: 337 - Can also include a quick lab tour to show HV-CMOS experimental setups (RD50-MPW4, UKRI-MPW1 and MightyPix)

RadPix submission plan (continuation) Room: 337

Progress since last in-person meeting Room: 337 - Summary of relevant measured results (RD50-MPW4, UKRI-MPW1 LFoundry prototypes) - Plans for TID evaluation at RAL in late October or November - We've never measured SEU tolerance

Anticipate DAQ Room: 337 - 'Standard' options are Caribou (used with RD50-MPW and UKRI-MPW), GECCO (MightyPix) and MARS (MightyPix) - Pros and cons of each option - What DAQ should we use to maximise the number of institutes contibuting to the evaluation programme?